During failure analysis (FA) of an integrated circuit (IC) chip, the user identifies a failing net, e.g. a portion of the IC netlist that is not properly functioning. The failure may be caused by a short or open circuit. To confirm the cause of the failure, the user may perform focused ion beam (FIB) operations to repair the failed portion of the chip. Such actions may include two types of FIB operations; i) cutting wires or nets and/or ii) depositing metal to connect wires. The FIB operations may be performed in FA processing or implemented inline in manufacturing processes for the IC. Performing a FIB operation is time consuming and costly for manufacturing processes and often it is a guess to find the failure location. Therefore the user may desire assurance of the electrical connectivity post-FIB and especially seeks to avoid damaging the circuit if it is for an inline FIB operation. Verifying the desired result of the FIB operation before physically performing the FIB operation on the IC is therefore desirable. Unfortunately, the success of current FIB operations is heavily dependent on the user's skills.
Accordingly, there is a need for an electronic design automation (EDA) tool to virtually verify intended FIB operations before the FIB operations are physically performed.